Fault-Tolerance in Nanocomputers: A Cellular Array Approach

Ferdinand Peper*, Jia Lee*, Fukutaro Abo, Teijiro Isokawa, Susumu Adachi*, Nobuyuki Matsui, and Shinro Mashiko*
* Communications Research Laboratory

Asynchronous cellular arrays have gained attention as promising architectures for nanocomputers, because of their lack of a clock, which facilitates low power designs, and their regular structure, which potentially allows manufacturing techniques based on molecular self-organization. With the increase in integration density comes a decrease in the reliability of the components from which computers are built, and implementations based on cellular arrays are no exception to this. This paper advances asynchronous cellular arrays that are tolerant to transient errors in up to one third of the information stored by its cells. The cellular arrays require six rules to describe the interactions between the cells, implying less complexity of the cells as compared to a previously proposed (nonfault-tolerant) asynchronous cellular array that employs nine rules.

IEEE Transactions on Nanotechnology, vol.3, no.1, pp.187-201 (2004).