3. Publications

(1)Easily Testable Multiple-Valued Cellular Arrays, Naotake Kamiura, Yutaka Hata, Fujio Miyawaki and Kazuharu Yamato, IEEE Proceedings of the 22nd International Symposium on Multiple-Valued Logic, Sendai, p.36 (1992).
(2)Design of a Multiple-Valued Cellular Array, Naotake Kamiura, Yutaka Hata and Kazuharu Yamato, IEICE Transactions on Electronics, Vol. E76-C, No. 3, p.412(1993).
(3)Design and Fault Diagnosis of Cellular Arrays Realizing Multiple-Valued Logic Functions, Naotake Kamiura, Yutaka Hata and Kazuharu Yamato, Transactions of the IEICE, Vol. J76-D-I, No. 12, p. 676 (1993) / Systems and Computers in Japan, Vol. 25, No. 9, p.41 (1994).
(4)A Repairable and Diagnosable Cellular Array on Multiple-Valued Logic, Naotake Kamiura, Yutaka Hata and Kazuharu Yamato, IEEE Proceedings of the 23rd International Symposium on Multiple-Valued Logic, Sacramento, USA, p.92 (1993).
(5)Design of Repariable Cellular Arrays on Multiple-Valued Logic, Naotake Kamiura, Yutaka Hata and Kazuharu Yamato, IEICE Transactions on Information and Systems, Vol. E77-D, No. 8, p. 877 (1994).
(6)Design of Fault-Tolerant Cellular Arrays on Multiple-Valued Logic, Naotake Kamiura, Yutaka Hata and Kazuharu Yamato, IEEE Proceedings of the 24th International Symposium on Multiple-Valued Logic, Boston, USA, p.297 (1994).
(7)Design in Fault Isolating of Ternary Cellular Arrays Using Ternary Decision Diagrams, Naotake Kamiura, Hidetoshi Satoh, Yutaka Hata and Kazuharu Yamato, IEEE Proceedings of the 3rd Asian Test Symposium, Nara, p.201 (1994).
(8)On Ternary Cellular Arrays Designed from Ternary Decision Diagrams, Naotake Kamiura, Hidetoshi Satoh, Yutaka Hata and Kazuharu Yamato, IEICE Transactions on Information and Systems, Vol. E78-D, No.4, p.326 (1995).
(9)A Cellular Array Designed from a Multiple-Valued Decision Diagram and Its Fault Tests, Naotake Kamiura, Yutaka Hata and Kazuharu Yamato, IEEE Proceedings of the 4th Asian Test Symposium, Bangalore, India, p.20 (1995).
(10)Multiple-Valued Logic Design Using Multiple-Valued EXOR, Takahiro Hozumi, Naotake Kamiura, Yutaka Hata and Kazuharu Yamato, IEEE Proceedings of the 25th International Symposium on Multiple-Valued Logic, Bloomington, USA, p.290 (1995).
(11)On Input Permutation Technique for Multiple-Valued Logic Synthesis, Yutaka Hata, Naotake Kamiura and Kazuharu Yamato, IEEE Proceedings of the 25th International Symposium on Multiple-Valued Logic, Bloomington, USA, p.170 (1995).
(12)On Design of Fail-Safe Cellular Arrays, Naotake Kamiura, Yutaka Hata and Kazuharu Yamato, IEEE Proceedings of the 5th Asian Test Symposium, Hsinchu, Taiwan (in press).
(13)Design and Fault Masking of Two-Level Cellular Arrays on Multiple-Valued Logic, Naotake Kamiura, Yutaka Hata and Kazuharu Yamato, IEICE Transactions on Information and Systems (in press).
(14)On Minimization of Multiple-Valued Sum-of-Products Expression with Multiple-Valued TRSUM, Takahiro Hozumi, Naotake Kamiura, Yutaka Hata and Kazuharu Yamato, Multiple-Valued Logic -An International Jounal- (in press).
(15)Design of MIN-of-TSUM Form Multiple-Valued PLA's Using Universal Literals, Takahiro Hozumi, Takashi Utsumi, Naotake Kamiura, Yutaka Hata and Kazuharu Yamato, Multiple-Valued Logic -An International Jounal- (in press).
(16)Design of Fuzzy PLAs Realizing Fuzzy Logic Functions, Yutaka Hata, Koji Takiguchi, Naotake Kamiura and Kazuharu Yamato, Japanese Journal of Fuzzy Theory and SAystems, Vol. 5, No.6, p.1312 (1993) / Allerton Press, p.871 (1995).
(17)An Application of Neural Computing to Fuzzy Logic Minimizer, Yutaka Hata, Laurent Lemitre, Takahiro Hozumi, Naotake Kamiura and Kazuharu Yamato, Proceedings of the 3rd Annual International Conference on Fuzzy-Neural Applications Systems and Tools, Burlingame, USA, p.42-1 (1995).
(18)An Improvement of the Fingerprint Identification System, Kazuharu Yamato, Toshihide Asada, Yutaka Hata and Naoteke Kamiura, Journal of the Institute of Image Electronics Engineers of Japan, Vol.24, No.4, p.382 (1995).

My paper published after 1996. (Click here!!!)

Note: IEICE in here is Japanese one.
IEICE : Institute of Electronics, Information and Communication Engineers in Japan