主な研究業績

学術論文及び国際会議発表

2010

• Characterization of Generation Lifetime and Surface Generation Velocity of Semiconductor Wafers by a Contactless Zerbst Method,

H. Yoshida and S. Kuge,
J. Electronic Materials Vol. 39, No. 6, pp. 773-776(2010)


• Contactless Frequency Domain Lifetime Characterization for Semiconductor Wafers,

K. Aoyagi and H. Yoshida,
Proc. of the 2010 Int. Meeting for Future of Electron Devices, Kansai, Osaka, IEEE, pp. 80-81(2010)


• Microscopic Interface Trap Characterization of Gate Stacks with Ultrathin High-k Films by Scanning Capacitance Microscopy,

J. Fujieda, S. Kuge, and H. Yoshida,
Proc. of the 2010 Int. Meeting for Future of Electron Devices, Kansai, Osaka, IEEE, pp. 84-85(2010)


• Characterization of Interface Traps in Ultrathin Gate Stacks by Contactless C-V Method,

A. Hashimoto, K. Aoyagi, and H. Yoshida,
Proc. of the 2010 Int. Meeting for Future of Electron Devices, Kansai, Osaka, IEEE, pp. 86-87(2010)

2009

• Local mapping of interface traps in HfSiO/Si structure by scanning capacitance microscopy using dV/dC signal,

S. Kuge and H. Yoshida,
J. Appl. Phys. Vol. 105, No. 9, p. 093708(2009)


• Carrier Lifetime Measurements of Semiconductors by Contactless Capacitance-Frequency Method,

H. Mori and H. Yoshida,
Abs. of the 13th Int. Conf. on Defects-Recognition, Imaging and Physics in Semiconductors, Wheeling, p. 4(2009)

2008

• First-Principles Calculation of Energy Band Structure of Gallium Arsenide Crystals Using Madelung Potential,

S. Kishino, K. Sueoka, and H. Yoshida,
Advances in Quantum Chemistry Vol.54, pp. 13-21(2008)


• Characterization of Carrier Lifetime in HfSiO/Si Structures using Contactless Capacitance Transient Technique,

M. Kawabata, S. Kuge, H. Yoshida, M. Inoue, and S. Satoh,
Proc. of the 2008 Int. Meeting for Future of Electron Devices, Kansai, Osaka, IEEE, pp. 87-88(2008)


• Carrier Lifetime Mapping using Contactless Capacitance Transient Technique,

S. Kuge, H. Yoshida, and S. Satoh,
Proc. of the 5th Int. Symp. on Advanced Science and Technology of Silicon Materials, Hawaii, JSPS, pp. 78-82(2008)


• Contactless Capacitance-Frequency Method for Carrier Lifetime Characterization of SOI Wafers,

H. Mori and H. Yoshida,
Proc. of the 5th Int. Symp. on Advanced Science and Technology of Silicon Materials, Hawaii, JSPS, pp. 285-289(2008)

2007

• Interaction of Stray Magnetic Field from Free and Pin Layers in MTJ,

T. Tokuami, H. Yoshida, K. Kawabata, and S. Satoh,
Proc. of The 2007 International Meeting for Future of Electron Devices, Kansai, Osaka, IEEE, pp. 109-110(2007)


• Local Characterization of Interface Properties of High-k Gate Stacks by Scanning Capacitance Microscopy,

S. Kuge, H. Yoshida, M. Inoue, and S. Satoh,
Proc. of The 2007 International Meeting for Future of Electron Devices, Kansai, Osaka, IEEE, pp. 111-112(2007)

2006

• Electrical Characterization of High-k Dielectrics/Si Interface by Contactless C-V Method,

K. Fukano, H. Yoshida, M. Inoue, and S. Satoh,
Proc. of The 2006 International Meeting for Future of Electron Devices, Kansai, Kyoto, IEEE, pp. 63-64 (2006)


• Energy Band Structure of Strained Semiconductor Studied by DVXα Calculation Uisng Madelung Potential [1],

S. Kishino, K. Sueoka, and H. Yoshida,
Proc. of the 4th International Conference on DV-Ｘα Method, Jeju, Bull. Soc. DV-Xα, Vol. 19, No. 1 & 2, pp. 210-216 (2006)

2005

• SOI Wafer Characterization and Gettering Aspects of SOI,

S. Kishino and H. Yoshida,
Crystalline Defects and Contamination; Their Impact and Control in Device Manufacturing IV, The Electrochem. Soc. Proc. Vol. 2005-10, pp. 93-105 (2005)

2004

• Photoluminescence mapping study of gettering effect of polycrystalline Si on ultrathin silicon-on-insulator,

Z. Q. Li, M. Tajima, N. Kitai, H. Yoshida, and S. Kishino,
Appl. Phys. Lett. Vol. 85, No. 23, pp. 5688-5690(2004)


• Microscopic C-V Measurements of SOI Wafers by Scanning Capacitance Microscopy,

T. Ishida, H. Yoshida, and S. Kishino,
The European Physical Journal - Applied Physics Vol. 27, No. 1-3, pp. 479-482(2004)


• Proposal of a Novel Gettering Technique for a Thin SOI Wafer,

S. Kishino, H. Yoshida, and N. Kitai,
Electrochem. and Solid-State Lett. Vol．7, No. 9, pp. G192-G194(2004)


• Improvement of SOI Device Characteristics by Gettering Procedure,

N. Kitai, H. Yoshida, S. Kishino, Z. Q. Li, and M. Tajima,
Proc. of the 5th European Workshop on Ultimate Integration of Silicon, Leuven, IEEE, pp.141-144(2004)


• Wafer Mapping of Bulk Traps in Silicon Using Scanning Capacitance Transient Spectroscopy,

T. Takahashi, H. Yoshida, and S. Satoh
Proc. of The 2004 International Meeting for Future of Electron Devices, Kansai, Kyoto, IEEE, pp. 95-96(2004)


• Carrier Lifetime Characterization of SOI Wafers Using Capacitance-Frequency Method,

K. Hara, H. Yoshida, S. Satoh, and S. Kishino
Proc. of the 4th International Symposium on Advanced Science and Technology of Silicon Materials, Hawaii, JSPS, pp. 326-331(2004)


• Improvement of Reliability of SOI Devices by a Novel Gettering Technique Using Polycrystalline Silicon,

H. Yoshida, N. Kitai, S. Satoh, and S. Kishino
Proc. of the 4th International Symposium on Advanced Science and Technology of Silicon Materials, Hawaii, JSPS, pp. 348-353(2004)


• Contactless Electrical Characterization for SOI Wafers,

T. Hasegawa, H. Yoshida, S. Satoh, and S. Kishino
Proc. of the 4th International Symposium on Advanced Science and Technology of Silicon Materials, Hawaii, JSPS, pp. 354-359(2004)


• Observation of Gettering Effect of Polycrystalline Si on Ultrathin Silicon-on-Insulator by Photoluminescence Mapping,

Z. Q. Li, H. Mitsuyama, M. Tajima, N. Kitai, H. Yoshida, and S. Kishino
Proc. of the 4th International Symposium on Advanced Science and Technology of Silicon Materials, Hawaii, JSPS, pp. 485-490(2004)

2003

• Correlation between Photoluminescence Lifetime and Interface Trap Density in Silicon-on-Insulator Wafers,

M. Tajima, H. Yoshida, S. Ibuka, and S. Kishino,
Jpn. J. Appl. Phys. Vol. 42, No. 4B, pp. L429-L431(2003)


• Modeling of the transient charge collection induced by an angled single ion strike,

H. Mori, T. Hirao, J. S. Larid, S. Onoda, T. Wakasa, T. Yamakawa, H. Itoh, T. Okamoto, and Y. Koizumi,
Nuclear Instruments and Methods in Physics Research B 206, pp. 31-35(2003)


• TCAD modeling of single MeV ion induced charge collection processes in Si devices,

J. S. Laird, T. Hirao, S. Onoda, H. Mori, and H. Itoh,
Nuclear Instruments and Methods in Physics Research B 206, pp. 36-41(2003)


• Displacement damage degradation of ion-induced charge in Si pin photodiode,

S. Onoda, T. Hirao, J. S. Laird, H. Mori, H. Itoh, T. Wakasa, T. Okamoto, and Y. Koizumi,
Nuclear Instruments and Methods in Physics Research B 206, pp. 444-447(2003)


• Study of single-event current pulses induced in SOI diodes by collimated swift heavy-ions micro-beams,

T. Hirao, H. Mori, J. S. Laird, S. Onoda, H. Abe, T. Wakasa, and H. Itoh,
Nuclear Instruments and Methods in Physics Research B 206, pp. 457-461(2003)


• Comparison of the ion induced charge collection in Si epilayer and SOI devices,

T. Hirao, H. Mori, J. S. Laird, S. Onoda, and H. Itoh,
Nuclear Instruments and Methods in Physics Research B 210, pp. 221-226(2003)


• Studies on single-event phenomena using the heavy-ion microbeam at JAERI,

T. Hirao, H. Mori, J. S. Laird, S. Onoda, T. Wakasa, H. Abe, and H. Itoh,
Nuclear Instruments and Methods in Physics Research B 210, pp. 227-231(2003)


• Estimation of fast transient current degradation analyzed by non-ionizing energy loss,

S. Onoda, T. Hirao, J. S. Laird, H. Mori, H. Itoh, T. Wakasa, T. Okamoto, and Y. Koizumi,
Nuclear Instruments and Methods in Physics Research B 210, pp. 232-236(2003)


• A comparison of heavy ion and picosecond laser microbeams for investigating single event transients in InGaAs on InP photodetectors,

J. S. Laird, T. Hirao, S. Onoda, H. Mori, and H. Itoh,
Nuclear Instruments and Methods in Physics Research B 210, pp. 243-249(2003)


• Characterization of Heavy Metal Contamination by Capacitance-Frequency Method,

K. Hara, M. Takahashi, H. Yoshida, and S. Kishino,
Analytical and Diagnostic Techniques for Semiconductor Materials, Devices, and Processes/ALTECH 2003, Paris, The Electrochem. Soc. Proc. Vol. 2003-03, pp.37-41(2003)

2002

• Preliminary Study of Novel Scanning Charge Pumping Method Using Extra Gates for Silicon-on-Insulator Wafer Inspection,

H. Yoshida, T. Takami, T. Uchihashi, S. Kishino, H. Naruoka, and Y. Mashiko,
IEEE Electron Device Lett. Vol. 23, No. 10, pp. 630-632(2002)


• 走査型容量顕微鏡による半導体材料のサブミクロン評価,

内橋貴之, 石塚義守, 吉田晴彦, 岸野正剛,
材料 Vol. 51, No. 9, pp. 995-998(2002)


• Local electrical characterization of SOI wafers by scanning probe microscopy,

Y. Ishizuka, T. Uchihashi, H. Yoshida, and S. Kishino,
Materials Science and Engineering Vol. B91-92, pp. 156-159(2002)


• Temperature dependence of heavy ion-induced current transients in si epilayer devices,

J. S. Laird, T. Hirao, S. Onoda, H. Mori, and H. Itoh,
IEEE Trans. Nuclear Science, Vol. NS-49, No.3, pp.1389-1395(2002)


• Spectral response of a gamma and electron irradiated pin photodiode,

S. Onoda, T. Hirao, J. S. Laird, H. Mori, T. Okamoto, Y. Koizumi, and H. Itoh,
IEEE Trans. Nuclear Science, Vol. NS-49, No.3, pp.1446-1449(2002)


• Characterization of SOI Wafer by Cross Sectional Scanning Probe Microscopy,

T. Uchihashi, Y. Ishizuka, H. Yoshida, and S. Kishino,
Semiconductor Silicon 2002 (9th), Philadelphia, The Electrochem. Soc. Proc. Vol. 2002-2, pp. 829-838(2002)


• Novel Charge Pumping Method without Using MOS Transistor for SOI Wafer Inspection,

T. Takami, H. Yoshida, T. Uchihashi, and S. Kishino,
Proc. of IEEE 2002 of International Conference on Microelectronic Test Structures, Cork, Vol. 15, pp. 183-187(2002)

2001

• Improvement of alignment tolerance against contact hole etching by growing of underlying silicon-selective epitaxial layer,

T. Nakahata, K. Sugihara, T. Furukawa, Y. Nishioka, S. Maruno, Y. Abe, Y. Tokuda, and S. Satoh,
Microelectronic Engineering Vol. 56, pp. 281-287(2001)


• Low thermal budget surface cleaning after dry etching for selective silicon epitaxial growth,

T. Nakahata, K．Yamamoto, J. Tanimura, T. Inagaki, T. Furukawa, S. Maruno, Y. Tokuda, A. Miyamoto, S. Satoh, and H. Kiyama,
J. Crystal Growth Vol. 226，pp. 443-450(2001)


• Surface defect formation in epitaxial Si grown on boron-doped substrates by ultrahigh vacuum chemical vapor deposition,

T. Furukawa, T. Nakahata, S. Maruno, J. Tanimura, Y. Tokuda, and S, Satoh,
Jpn. J. Appl. Phys., Vol. 40, pp. L1051-L1053(2001)


• Electron beam writing methods of x-ray masks for eliminating thermal image placement errors,

K. Kise, S. Aya, H. Yabe, S. Ami, K. Marumoto, S. Satoh, and H. Watanabe,
J. Vaccum Science & Technology B，Vol. 19，pp. 1728-1733(2001)


• Bipolar Transistor Selected P-channel Flash Memory Cell Technology,

Ｔ. Ohnakado, N. Ajika, and S, Satoh,
IEEE Trans. Electron Devices, Vol.48, pp. 863-867(2001)


• Back-channel-type scanning charge pumping method for characterization of interface traps in silicon-on-insulator wafer,

H. Yoshida, H. Sasakura, T. Yabuuchi, T. Takami, T. Uchihashi, and S. Kishino,
Appl. Phys. Lett. Vol. 79, No. 12, pp. 1825-1827(2001)


• Electrical Characterization of Thin SOI Wafer,

S. Kishino, H. Yoshida, and T. Uchihashi,
Crystalline Defects and Contamination: Their Impact and Control in Device　Manufacturing III, Nuremberg, The Electrochem. Soc. Proc. Vol. 2001-29, pp. 143-152(2001)

2000

• Evaluation of exposure dose repeatability in synchrotron radiation lithography,

K. Itoga, H. Sumitani, H. Watanabe, T. Kumada, I. Kodera, S. Satoh, N. Ogushi, S. Oishi, R. Edo, T. Yamamoto, and Y. Watanabe,
J. Vacuum Science & Technology B, Second series, Vol. 18, No. 2, pp. 774-779(2000)


• Novel self-limiting high-speed program scheme of P-channel DINOR flash memory with N-channnel select transistors,

T. Ohnakado, and S. Satoh,
IEEE Trans. Electron Devices，Vol. 47, No. 6, pp. 1209-1213(2000)


• Selective epitaxial growth by ultrahigh-vacuum chemical vapor deposition with alternating gas supply of Si2H₆ and Cl₂,

S. Maruno, T. Nakahata, T. Furukawa, Y. Tokuda, S. Satoh, K. Yamamoto, T. Inagaki, and H. Kiyama,
Jpn. J. Appl. Phys., Vol. 39, pp. 6139-6142(2000)


• Frequency Domain Lifetime Characterization,

D. K. Schroder, J. E. Park, S. E. Tan, B. D. Choi, S. Kishino, and H. Yoshida,
IEEE Trans. Electron Devices Vol. 47, No. 8, pp. 1653-1661(2000)


• Sensitivity of contactless transient spectroscopy and actual measurement of localized states in oxidized Si wafer,

H. Yoshida, R. Nakanishi, and S. Kishino,
J. Crystal Growth Vol. 210, pp. 379-383(2000)


• Characterization of Deep Levels in Si-MOS Structure using ICTS Measurement,

S. Iwamoto, H. Yoshida, and S. Kishino,
Electrical Engineering in Japan Vol. 130, No. 4, pp. 76-86(2000)


• A new cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a Pt-Ir alloy coating,

H. Itoh, Y. Tsunemine, A. Yutani, T. Okudaira, K. Kashihara, M. Inuishi, M. Yamamuka, T. Kawahara. T. Horikawa, T. Ohmori, and S. Satoh,
VLSI Tech. Symp., Tech. Dig., pp. 106-107(2000)


• Proposal of Scanning Charge Pumping Method for Characterization of Localized States in SOI Wafers,

H. Yoshida, T. Uchihashi, H. Naruoka, Y. Mashiko, and S. Kishino,
Proc. of the 3rd International Symposium on Advanced Science and Technology of Silicon Materials, Hawaii, JSPS, pp. 605-611(2000)


• Characterization of SOI Wafer at Nanometer Scale using Scanning Probe Technique,

T. Uchihashi, H. Yoshida, and S. Kishino,
Proc. of the 3rd International Symposium on Advanced Science and Technology of Silicon Materials, Hawaii, JSPS, pp. 612-617(2000)

特許

佐藤教授

• 半導体装置,

伝田，佐藤，坪内,
登録番号　JP1384618（1987）


• 半導体集積回路装置,

佐藤,
登録番号　JP1896333（1995）


• 配線構造を有する半導体装置,

佐藤,
登録番号　JP2104762（1996）


• 半導体装置の製造方法,

栄森，佐藤，若宮，小崎，田中,
登録番号　JP2507557（1996）


• 半導体装置,

木村，佐藤，小崎，田中，若宮,
登録番号　JP2038749（1996）


• 半導体装置及びその製造方法,

佐藤，小崎，木村，若宮，田中,
登録番号　JP2598328（1997）


• 半導体記憶装置のキャパシタ及びその製造方法,

若宮，小崎，田中，栄森，木村，佐藤,
登録番号　JP2838412（1998）


• Stacked capacitor for semiconductor memory device,

W. Wakamiya, Y. Tanaka, T. Eimori, H. Ozaki, H. Kimura, S. Satoh,
United States Patent No. 5047817(1991)


• Field effect transistor with T-shaped gate electrode,

S. Satoh, H. Ozaki, T. Eimori,
United States Patent No. 5089863(1992)


• Semiconductor device having bonding pad comprising buffer layer,

S. Satoh, H. Ozaki, H. Kimura, W. Wakamiya, Y. Tanaka,
United States Patent No. 5084752(1992)

吉田准教授

• 半導体ウエハの特性評価装置及びその使用方法,

岸野正剛，吉田晴彦，内橋貴之,
登録番号　3448040（2003）


• 半導体ウェファの局在準位測定装置及び方法,

岸野正剛，吉田晴彦,
登録番号　3566648（2004）


• 半導体ウェーハの不純物除去方法及び半導体装置,

長友良樹，岸野正剛，吉田晴彦，田島道夫,
公開番号　2005-129559（2005）

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